{"id":56347,"date":"2024-06-18T15:04:12","date_gmt":"2024-06-18T15:04:12","guid":{"rendered":"https:\/\/www.threatshub.org\/blog\/cheri-alliance-formed-to-promote-memory-security-tech-but-wheres-arm\/"},"modified":"2024-06-18T15:04:12","modified_gmt":"2024-06-18T15:04:12","slug":"cheri-alliance-formed-to-promote-memory-security-tech-but-wheres-arm","status":"publish","type":"post","link":"https:\/\/www.threatshub.org\/blog\/cheri-alliance-formed-to-promote-memory-security-tech-but-wheres-arm\/","title":{"rendered":"CHERI Alliance formed to promote memory security tech … but where’s Arm?"},"content":{"rendered":"

A group of technology organizations has formed the CHERI Alliance CIC (Community Interest Company) to promote industry adoption of the security technology focused on memory access.<\/p>\n

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We will also work with the industry to reach common ground when it comes to specifications for how to implement CHERI<\/p>\n<\/blockquote>\n

The CHERI Alliance<\/a> hopes to drive the adoption of enhanced security, with its initial members comprising the FreeBSD Foundation, security consultancy outfits Capabilities Limited and SCI Semiconductor, chip designers Codasip and lowRISC, and the University of Cambridge<\/a>, which is one of the prime movers behind the technology.<\/p>\n

CHERI, or Capability Hardware Enhanced RISC Instructions, comprises instruction-set extensions that implement fine-grained memory protections in CPU hardware. This technology aims to combat common vulnerabilities such as buffer overflows and the misuse of pointers via use-after-free errors.<\/p>\n

\"Arm<\/p>\n

How Arm popped CHERI architecture into Morello Program hardware<\/h2>\n

READ MORE<\/span><\/a><\/div>\n

It is the result of a research project between the University of Cambridge and US-based research institute SRI International. Because it can be applied selectively to critical functions and requires almost negligible software modifications, the security of existing applications can be enhanced with minimal effort, if the hardware support is in place.<\/p>\n

According to the CHERI Alliance, its governing board is set to include representatives from industry as well as academia, with the aim of galvanizing industry leaders, system developers, users, and security experts to drive and promote CHERI as an efficient security standard.<\/p>\n

“As noted by the White House in a recent report on a path toward secure and measurable software, hardware support is critical to robust and efficient memory safety. Compiling software to run on CHERI enhanced processors guarantees very strong memory safety that an attacker cannot bypass,” University of Cambridge Professor Simon Moore said in a statement.<\/p>\n

However, one notable name missing from the list of CHERI Alliance initial members is chip designer Arm, which has also played a key role in the development and promotion of CHERI.<\/p>\n