{"id":33737,"date":"2020-03-09T21:10:13","date_gmt":"2020-03-09T21:10:13","guid":{"rendered":"https:\/\/www.threatshub.org\/blog\/amd-boffins-clash-over-chip-data-leak-claims-side-channel-holes-revealed-in-decade-of-processors\/"},"modified":"2020-03-09T21:10:13","modified_gmt":"2020-03-09T21:10:13","slug":"amd-boffins-clash-over-chip-data-leak-claims-side-channel-holes-revealed-in-decade-of-processors","status":"publish","type":"post","link":"https:\/\/www.threatshub.org\/blog\/amd-boffins-clash-over-chip-data-leak-claims-side-channel-holes-revealed-in-decade-of-processors\/","title":{"rendered":"AMD, boffins clash over chip data-leak claims: Side-channel holes revealed in decade of processors"},"content":{"rendered":"

AMD processors sold between 2011 to 2019 are vulnerable to two side-channel attacks that can extract CPU kernel data and secrets, according to a new research paper.<\/p>\n

In a paper<\/a> [PDF] titled, “Take A Way: Exploring the Security Implications of AMD\u2019s Cache Way Predictors,” six boffins \u2013 Moritz Lipp, Vedad Had\u017ei\u0107, Michael Schwarz, and Daniel Gruss (Graz University of Technology), Cl\u00e9mentine Maurice (University of Rennes), and Arthur Perais (unaffiliated) \u2013 explain how they reverse-engineered AMD\u2019s L1D cache way predictor to expose sensitive data in memory.<\/p>\n

To save power when looking up a cache line in a set-associative cache, AMD relies on way prediction. The way predictor allows the CPU to check the cache tag one way instead of wasting power on checking all the multiple ways a cache can be configured. This speeds up operations, though it can also add latency when misprediction occurs.<\/p>\n

The cache tag is produced by a hash function, undocumented by AMD, that hashes the virtual address of the memory load. By reverse engineering this hash function, the researchers were able to create tag collisions which present observable timing effects \u2013 increased access time or L1 cache misses \u2013 that allow covert kernel data exfiltration, cryptographic key recovery, and weakening ASLR defenses on a fully-patched Linux system, the hypervisor, or the JavaScript sandbox.<\/p>\n

Timing attacks of this sort allow the attacker to infer protected data based on the time the system takes to respond to specific inputs.<\/p>\n

\"Chip\"<\/p>\n

Cache flow problems continue for Intel: Yet more data-leaking processor design blunders discovered, patches due soon<\/h2>\n

READ MORE<\/span><\/a><\/div>\n

The two attacks are called Collide+Probe and Load+Reload, in reference to the operations involved. The former exploits tag collisions while the latter exploits the way predictior’s behavior for virtual addresses are mapped to the same physical address.<\/p>\n

“With Collide+Probe, an attacker can monitor a victim\u2019s memory accesses without knowledge of physical addresses or shared memory when time-sharing a logical core,” the paper explains, noting that the technique has been demonstrated with a data transmission rate of up to 588.9 kB\/s. “With Load+ Reload, we exploit the way predictor to obtain highly-accurate memory-access traces of victims on the same physical core.”<\/p>\n

For Collide+Probe, the attacker is assumed to be able to run unprivileged native code on the target machine that’s also on the same logical CPU core as the victim. It’s also assumed the victim’s code will respond to input from the attacker, such as a function call in a library or a system call.<\/p>\n

For Load+Reload, the ability to run unprivileged native code on the target machine is also assumed, with the attacker and victim on the same physical but different logical CPU thread.<\/p>\n

Local access is not a requirement for these attacks; the researchers demonstrated their techniques on sandboxed JavaScript and a virtualized cloud environments.<\/p>\n

The boffins said that the following AMD chips have a way predictor that can be abused:<\/p>\n